Dr. Mohan Kumar Naik
Educational Qualification:
B.E. : Electronics and Communication Engineering
M.Tech : VLSI Design and Embedded Systems.
PhD : Electronics and Communication Engineering (Low Power VLSI Design)
Total Experience : 22 years
Professional Memberships : MISTE
Area of Interest
Real Time System Design
FPGA
Mechatronics System Design
VLSI Design (Front end and Back end)
Subjects Handled : Embedded Systems
Real Time Systems
MSMT
CMOS VLSI Design
Low power VLSI Design
Power Electronics.
Summary of Research and Publications;
Book/ Chapter Publications:
- SOI FinFET-Based 6T SRAM Design, Soft Computing and Signal Processing, Advances in Intelligent Systems and Computing 1413, https://doi.org/10.1007/978-981-16-7088-6_4. Springer Nature Singapore Pte Ltd. 2022.
- “Analysis and Forecast of Heart Syndrome by Intelligent Retrieval Approach (Springer Book), Intelligent Computing and Innovation on Data Science. ISBN 978-981-15-3283-2 ISBN 978-981-15-3284-9 (eBook).
- “Design and Modelling of Different Types of SRAMs for Low-Power Applications”.(Springer Book), Advances in Intelligent Systems and Computing. ISBN 978-981-13-3392-7 ISBN 978-981-13-3393-4 (eBook).
International/ National Journal and Conference Publications:
- Analysis of Academic Performance in massive Open Online Courses (Moocs) Using Process Mining. International Journal of Computer Trends and Technology Volume 68 Issue 12, 21-25, December 2020 ISSN: 2231 – 2803 /doi:10.14445/22312803/IJCTT-V68I12P105.
- A Comprehensive Review of Behavioral Customer Segmentation for A Better Understanding, SSRG International Journal of Computer Science and Engineering Volume 8 Issue 1, 1-4, January 2021 ISSN: 2348 – 8387 /doi:10.14445/23488387/IJCSE-V8I1P101
- “Comparison Analysis Of N-Channel And P-Channel SOI/ Bulk Finfets,” International Journal of Scientific & Technology Research VOLUME 9, ISSUE 01, JANUARY 2020 ISSN 2277-8616 (Scopus Journal).
- “Analytical Modeling and Simulation of FinFET for Semiconductor memories”. ICIREMS-2019, International Conference (Scopus Journal).
- “An Average power Estimation Technique for Integrated Circuits”. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 7, Issue 5, Ver. I (Sep-Oct. 2017), PP 27-29.
- “Glitch Elimination and Optimization of Dynamic Power Dissipation in Combinational Circuits”. IEEE Digital Xplore.
- “Automated Shopping Cart”, McGraw-Hill publication, International Conference
- “Content Based Image Retrieval using Color and Texture Content” International Journal of Computer Trends and Technology (IJCTT), UGC Approved
- “A CMOS Combinational Logic Gates Power Estimation Technique “. International Journal of Electronic Engineering Research. UGC Approved
- “Rfid and Zigbee Based Intelligent Traffic Control System” International Journal of Computer Engineering and Applications, UGC Approved
- “Digital VLSI Circuit Low Power Estimation Technique”. International Journal of Electronics Communication Engineering. UGC Approved
- “A Low power Estimation Technique for Logic gates in VLSI” International Journal of Engineering and Innovative Technology
- “Delay Estimation and Optimization of a VLSI CMOS Circuits” International Journal of Electronic Engineering Research. Research India Publications
- “Digital VLSI Circuits Power Estimation Technique”. International Conference
- “Maximum power Estimation Technique for CMOS – VLSI Circuits” International Conference
- “Key Scanner Board Design Using Xilinx FPGA”. International Conference
- “Extending Multicore Interconnect Architecture to Increase the performance of Processors”. At National conference
- “Estimation of Gate Level Dynamic Power Dissipation Due to Glitch” at National conference
- “Delay Estimation and Optimization of a Clocked CMOS Inverter”. at National conference
- “An OFDM Based System for Transmission of JPEG2000 Images Using Unequal Power allocation” at National conference.
- “Touch the Virtual Reality Objects”. at National conference.
- “LIFI Technology: Finding in Advanced Applications”. at National conference.