Dr. Rashmi K M
Educational Qualification
Ph.D
Total Experience
06 Years
Area of Interest
- Low power VLSI Testing
- VLSI fault diagnosis
- VLSI based DAQ modelling
- VHDL based fault simulation
Subjects Handled
- Control system
- Analog and mixed mode VLSI
- Management and entrepreneurship
- Virtual instrumentation
- ASIC design
- Low power VLSI
- Basic Electronics
- Information technique and coding
Conference/Journal Publication
- KM, Dr.K.N.Muralidhara, ”Design of Scan Chain using Level Sensitive Flip-Flops for VLSI Testing”, International journal of Advanced Science and Technology, ISSN: 2005-4238,vol. 29, No. 7(2020),pp-2352-2357. http://sersc.org/journals/index.php/IJAST/article/view/17973
- KM, Dr.K.N.Muralidhara,.”Design of Low Power Hybrid Model for scan based VLSI Testing”, Journal of TEST Engineering and Management ISSN: 0193-4120 Vol.81, Issue Nov-Dec 2019, pp.5101-5107. http://testmagzine.biz/index.php/testmagzine/article/view/711
- KM, Dr.K.N.Muralidhara,.”Efficient scan chain masking and re-ordering for diagnosis of multiple faults in VLSI circuits”, Journal of Emerging Technologies and Innovative Research (JETIR) ISSN: 2349-5162 Vol.5, Issue 12, Dec 2018. https://www.jetir.org/view?paper=JETIR1812606
- KM, Dr.K.N.Muralidhara,. “Survey of scan chain based low power testing”, International Journal of Science and Engineering Development Research (IJSDR) ISSN: 2455-2631 Vol. 1, Issue 7, July 2016. https://www.semanticscholar.org/paper/Survey-of-Scan-Chain-based-Low-Power-Testing-Muralidhara/f39bd2ea725c0c6bdefedfbb494acbef430db8a4
- KM et al. “FPGA Implementation of Efficient Algorithm of Image Splitting for Video Streaming Data”, International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1244-1247.
- Rashmi KM et al. “FPGA BASED DATA ACQUISITION SYSTEM”, International conference on VLSI and Signal Processing (ICVSP), KSIT Bangalore, May 4,5th 2012.