Dr. Suhas B. Shirol

Dr. Suhas B. Shirol

Position: Assistant Professor
Phone: 9035203578
Email: suhasshirol@mite.ac.in

Educational Qualification

  • B.E (Electronics & Communication Engineering)
  • M.Tech (VLSI Design & Testing)
  • Ph.D – in area of VLSI

Experience

  • Teaching : 13 Years 5 months
  • Industry : 1 Year 6 months                             :

Area of Interest

Digital VLSI, VLSI Testing, ASIC Design, Design for Testability and AI/ML for VLSI

Professional Membership

IEEE:

ISTE:

  • Others:
    Institute of Engineers (AM1916974)
  • International Association of Engineers (315466)

Orcid ID

https://orcid.org/0000-0002-3996-542X

Publons ID

AAV-5460-2020

Scopus ID

57192556601

Google Scholar ID

https://scholar.google.com/citations?hl=en&user=V4E64ZMAAAAJ&view_op=list_works&authuser=1&sortby=pubdate

Vidwan ID

153687

Subjects handled

  • CMOS VLSI Circuits
  • CMOS ASIC Design
  • DSD using Verilog
  • Advance Architectural Design
  • Digital IC Design
  • ARM Microcontroller
  • Microcontroller
  • VLSI Testing and Verification

Workshop/FDP/STTP Attended

  1. Attended Two-Week Online Professional Development Programme on “AI-Driven VLSI Design and Optimization” organized by the Department of Electronics & Communication Engineering & MUJ-TEC, Manipal University Jaipur, from 7th July 2025 to 18th July 2025.
  2. Attended one week Training Program on “FOUNDATION OF VLSI TESTING & DESIGN FOR TEST” from 26th Dec. to 30th Dec. 2024 at IIIT,Dharwad.
  3. Attended One Week AICTE Workshop on “VLSI to system Design: Silicon to End Application Approach”  from 31st  to 4th  Aug. 2023
  4. Attended short term training program on “Connecting People to the Semiconductor Industry” , conducted by SRM Institute of Science and Technology, from 5th – 17th Dec. 2022
  5. Attended One Week Online Training Programme on “Advanced Physical Design using OpenLANE/SKY130”, conducted by VLSI System Design, from 3rd -7th August 2022.
  6. Attended One Week Online Training Programme on “RISC-V based MYTH” conducted by Redwood EDA and OSFPGA Foundation in collaboration with VLSI System Design, from 25th -30th May 2022.
  7. Attended One Week Online Training Programme on “FPGA-Fabric, Design and Architecture” conducted by VLSI System Design, from 23rd -27th March 2022.

Participated in 50+ trainings that include technical and personality development program

Industrial Training Attended

  1. VLSI Design Methodologies(Maven Silicon)- 7 Weeks
  2. VLSI SYSTEM DESIGN USING OPEN SOURCE EDA (E&ICT Academy IIT Guwahati in association with VLSI System Design (VSD) Corp. Pvt. Ltd.) – 5 days
  3. Industry Academia Connect Hands-on Training Program on RBEI Customized Embedded System Kit”, at RBEI – Electronic city campus
  4. Workshop on “PCB Design & Technologies” conducted by Clik Technology at Mangalore
  5. UTLP Practitioner Training Program” conducted by Wipro Technologies at Bangalore

Conference Publications

  1. Kademani, S. Shirol, S. Siddamal, and H. M. Vijay, “GUI implementation of logic built-in self-test,” in Proc. IEEE INOCON, pp. 1–6, 2024.
  2. Gavimath et al.,S. B. Shirol “FPGA implementation of vector reduction algorithm for LFSR,” in Congress on Control, Robotics, and Mechatronics, pp. 197–205, 2024.
  3. B. Shirol, S. Ramakrishna, and R. B. Shettar, “Reinforcement learning for energy efficiency in 5G networks with BIST architecture,” in World Conf. Information Systems for Business Management, pp. 253–264, 2024.
  4. G. Patil and S. Shirol, “Implementation of memory built-in self-test,” in Proc. IEEE ITC-India, pp. 1–4, 2025.
  5. Waddar, A. A. Patil, G. Korimath, R. Kalyani, S. Shirol, and N. C. Iyer, “ESP32-driven real-time indoor localization using Wi-Fi RSSI and a simple path loss model,” in Proc. IEEE Int. Conf. Emerging Technologies in Computing and Communication (ETCC), pp. 1–6, 2025.
  6. Ullagaddi, S. Shirol, S. Sheth, P. Aski, M. Srushti, V. S. Saroja, H. M. Vijay, and M. Rajeshwari, “Design of different LFSRs for area, power, and delay analysis,” in Int. Conf. Information and Communication Technology for Competitive Strategies, pp. 31–40, 2024.
  7. D. Prabhu, S. Shirol, S. Prabhu, L. A. K. Reddy, L. Muttagi, T. Rakesh, V. S. Saroja, and V. B. Suneeta, “Smart street light for sustainable cities,” in Int. Conf. Information and Communication Technology for Competitive Strategies, pp. 21–29, 2024.
  8. Rachanna, S. Shirol, S. Sonal, M. Srushti, P. Aski, V. S. Saroja, H. M. Vijay, and M. Rajeshwari, “Design and implementation of Dadda multiplier in 45 nm technology,” in Int. Conf. Information Technology and Intelligence, pp. 127–137, 2024.
  9. Anushree, H. M. Kelagadi, K. Sphoorti, P. Gajanan, P. Nilesh, and S. Shirol, “Smart living, sustainable future: Enhancing homes with automation and energy meters,” in Int. Conf. Information and Communication Technology for Competitive Strategies, pp. 49–60, 2024.
  10. Shirol, S. Ramakrishna, and R. B. Shettar, “Designing power-efficient BIST architecture: Leveraging reversible logic for scalable digital systems,” J. Electrical Systems, vol. 20, no. 2, pp. 2747–2762, 2024.
  11. S. Neelakanthmath, S. Ramakrishna, S. B. Shirol, and S. S. Kotabagi, “Implementation of Hamming code technique in high-capacity memory module,” in Int. Conf. Data Science and Communication, pp. 345–354, 2024.
  12. V. Amoghimath, H. M. Vijay, and S. B. Shirol, “Neuromorphic computing using RRAM,” in Int. Conf. Emerging Trends in Microelectronics, Communication and Intelligent Systems, pp. 99–120, 2024.
  13. Aman Kotagi, B. Shirol, A. Amith, P. Angadi, A. S. Vimalnath, V. S. Saroja, H. M. Vijay, and M. Rajeshwari, “BIST architecture using different pattern generators,” in Int. Conf. Data Science and Communication, pp. 319–328, 2024.
  14. More, S. Shirol, A. Bandiwad, and N. G. M., “Design and implementation of Braun multiplier with different adder architectures,” in ITM Web of Conferences, vol. 79, Art. no. 01009, 2025.
  15. Inamati, G. Naragund, C. Paranatti, S. V. Siddamal, S. Shirol, H. M. Vijay, and S. Budihal, “Design and implementation of cyclic redundancy check for downlink transmission in NB-IoT,” in Int. Conf. Emerging Trends in Microelectronics, Communication and Intelligent Systems, pp. 53–62, 2024.
  16. K. R., M. S. Ullagaddi, S. Mirajakar, S. Shirol, and A. Telgar, “Multimodal multilingual translation system with text, voice, and visual outputs,” in Proc. Int. Conf. INSPIRE, pp. 465–469, 2025.
  17. G. Patil, N. Shetty, M. Mahadevappa, N. Balse, S. Shirol, and A. Telgar, “Region-aware image enhancement using SRGAN on DIV2K dataset,” in Proc. Int. Conf. INSPIRE, pp. 174–177, 2025.
  18. Dandoti, R. Ullagaddi, A. K., S. Shirol, and S. V. Budihal, “Design and verification of serial communication protocols using SystemVerilog,” in Proc. Innovations in Power and Advanced Computing Technologies (i-PACT), pp. 1–7, 2025.
  19. R. Vernekar, V. D. Chitragar, L. Koutanali, P. Sangalad, H. M. Kelagadi, and S. B. Shirol, “Automatic irrigation and tank water monitoring system,” in Int. Conf. ICT for Sustainable Development, pp. 498–508, 2025.
  20. Manupriya, M. Rajeshwari, G. Haripriya, B. Hema, S. V. Siddamal, H. M. Vijay, S. Shirol, and I. Ganga, “FPGA implementation of AES algorithm,” in World Conf. Information Systems for Business Management, pp. 356–367, 2025.

Journals Published 

  1. Shirol, “Scalable Logic BIST Design and Analysis for Enhanced Testing of Combinational Circuits,” Proceedings on Engineering Sciences, Jan. 2024.
  2. Shirol, “Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems,” Journal of Electrical Systems, Apr. 2024.
  3. Shirol, “Towards Sustainable Integrated Model for Skill Development: A Collaborative Approach,” in Proc. 9th World Engineering Education Forum (WEEF), Jan. 2020.
  4. Shirol, “Industry-Institute Interaction: An Important Step Towards Empowering Skills of Engineering Students,” in Proc. 2nd Int. Conf. Transformations in Engineering Education (ICTIEE), Jan. 2015.
  5. Shirol, “Design and Implementation of Different Type of Adders Using Bit Swapping LFSR as Delay Improvement,” Int. Res. J. Eng. Technol. (IRJET), Jan. 2017.
  6. Shirol, “A Comparative Study of Low Power Testing Techniques for Digital Circuits,” Int. J. Adv. Res. Comput. Sci. Softw. Eng., Jan. 2017.
  7. Shirol, “Design and Characterization of High-Speed Carry Select Adder,” Int. J. Ethics Eng. Manag. Educ., Jan. 2014.

Resource Person at Faculty Development / Student Development Program

  1. Internship Program on VLSI Design (1 Month), P. C. Jabin Science College (Electronics Dept.), hosted at KLE Technological University, Apr.–May 2025.
  2. Student Training Program on VLSI Design Flow using Cadence (C2S Program, MeitY), Feb. 2024.
  3. Workshop on VLSI Design using Cadence for faculty of P. C. Jabin Science College, Hubli, Dec. 2023.
  4. Faculty Development Program on VLSI and Communication Systems, School of ECE, KLE Technological University, Hubli, Sept. 2023.
  5. FDP on Real-Time System Development on ARM Platform using RTX Kernel & Custom IC Design using CADENCE Virtuoso IC6, ECE Dept., B.V. Bhoomaraddi College of Engg. & Tech., Hubli, Oct. 2016.
  6. Workshop on Technical Report Writing in LaTeX & Digital and Analog VLSI Design using Cadence, ECE Dept., B.V. Bhoomaraddi College of Engg. & Tech., Hubli, Sept. 2016.

Faculty Development Programme (Organized)

  1. FDP on Vivado Design Flow and Accelerators, School of Electrical & Electronics Engg., KLE Technological University, Hubli, Feb. 2025.
  2. FDP on VLSI and Communication Systems, School of ECE, KLE Technological University, Hubli, Sept. 2023.
  3. FDP on ARM Microcontroller Programming and Control Systems, School of ECE, KLE Technological University, Hubli, May 2023.
  4. FDP on FPGA-Based Deep Learning Applications in Signal Processing, School of ECE, KLE Technological University, Hubballi, Jul. 2021.
  5. FDP on Chisel Programming, School of ECE, KLE Technological University, Hubballi, Aug. 2019.
  6. FDP on Embedded Linux Programming and Application Development on ARM Platform, School of ECE, KLE Technological University, Hubballi, Aug. 2018.

Research Grants Received

AICTE Sponsored 5 Days ATAL FDP on FPGA-Based Deep Learning Applications in Signal Processing – Rs. 93,000/-

Patent Published

  • IN Patent 202241038728, Dynamic S-Box for N-Bit AES
  • IN Patent 202241038798, SCALABLE Built-In Self-Test (BIST) FOR TESTING OF DIGITAL CIRCUITS USING REVERSIBLE LOGIC
  • IN Patent 202241004343, Cloud Computing-Based Techniques To Track The Cabs

Achievements

  • Best Paper award in IEEE ComputingCon Conference – 2025
  • Best Paper award in the Academic track in India Test Conference(ITC) – 2025
  • Evaluator in ‘Toycathon, 2021′, AICTE and Ministry of Education Innovation Cell
  • Certificate of Appreciation for Project guidance in the “5th National Level IEEE Project Competition- 2021”, (4 Projects)
  • Part of 2 Chip Tapeout at KLE Technological University
  • Certificate of Appreciation for 5 papers published in WoS / Scopus Indexed during 2019

Funded Project Details

NA