tharanath-h-b

Mr. Taranath H B

Position: Senior Assistant Professor
Phone: #

Educational Qualification     

B.E- Electronics and Communication Engineering 

M.Tech- VLSI Design & Embedded Systems

Experience                          

9.5 Years(Teaching)

Area of Interest                

Design of VLSI Systems, CMOS Circuit Design and  Analog CMOS IC

 Professional Membership            

  • The Institute for Computer Sciences, Social Informatics and Telecommunications Engineering (ICST)
  • Indian Society of Technical Education (ISTE) :
  • Institute of Electrical and Electronics Engineers (IEEE): 93921533
  • The International Association of Engineers (IAENG)

 Subject Handled              

  • Analog Electronic Circuits
  • Fundamentals of CMOS VLSI
  • Microelectronic Circuits, Basic Electronics
  • Embedded Systems
  • Synthesis and Optimization of Digital Circuits
  • Advanced VLSI Design
  • Digital VLSI Design, Digital electronics
  • VLSI Design
  • Verilog HDL and Digital System Design

  Workshops / FDPs / SDPs / STTPs Attended/Conducted 

   22

Conference / Journal Publications 

International Journals

  • Chithrakshi and Taranath H. B, “Image Compression Using Fuzzy Enhancement,” International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249-8958, Volume-3, Issue-4, April 2014
  • Nikunj Acharya and Taranath H. B, “Design of Digital FIR Filter using MCM Technique,” International Journal of Research (IJR), ISSN: 2348-6848, Volume-2, Issue-5, May 2015
  • Asha and Taranath H. B, “Active Q Control of an AFM Micro Cantilever Using PPF Controller,” International Journal of Electrical and Electronics Research ISSN 2348-6988 (online) Vol. 3, Issue 1, pp: (341-345), Month: January – March 2015
  • Asha and Taranath H. B, “Analysis of Active Q Control of an AFM Micro Cantilever,” International Journal of Electrical, Electronics and Computer Systems (IJEECS-2015), ISSN (Online):2347-2820, Volume-3, Issue-6., May 2015
  • Taranath H B, Velen Ruben Aranha, Rajesh Kamath. (2020). A Review on Power Reduction Techniques in Low Power VLSI Design. International Journal of Advanced Science and Technology, 29(7), 11162-11168.

International Conferences

  •  Yashvanth K. S and Taranath H. B, “An Implementation of Built-In Repair Analyzer for Word-Oriented Memories using Parallel Prefix Algorithm,” Proc. Of Int. Conf. on Recent Trends in Signal Processing, Image Processing and VLSI, ICrtSIV-2014., Feb 2014
  • Asha and Taranath H. B, “Active Q control of an AFM microcantilever using piezoelectric shunt control,” Second International Conference on Recent Advances in Science & Engineering-2015, ISBN: 978-93-84935-32-0 (ICRASE-2015)., May 2015

National Conferences

  •  Taranath H. B and Arun kumar M, “Buffer Overflow Attack Protection for Embedded System,” Conf. on Evolutionary Trends in Information and Technology CETIT-2011., May 2011
  • Sowmya Bhat and Taranath H. B, “Design of area efficient ARM7 processor core using VHDL,” National Conference on Communication & Image Processing NCCIP-2014., May 2014
  • Chithrakshi and Taranath H. B, “Direct Approach of Designing Fuzzy logic Based System,” National Conference on Communication & Image Processing NCCIP-2014., May 2014

 

Funded Projects 

The project titled “Automatic automotive gear prediction system”, received a grant of Rs. 7000 from Karnataka State Council for Science & Technology in the year 2019.