Mr. Uday J


Mr. Uday J

Position: Senior Assistant Professor
Phone: #

Educational Qualification    

B.E-Electronics and Communication Engineering

M.Tech-Digital Electronics and Communication System


6 Years(Teaching) +1 year (Industry)

Area of Interest            

 Digital Circuit Design, Image Processing

Subject Handled               

  • HDL
  • DSP
  • DSDV
  • Basic Electronics
  • Satellite Communication
  • Wireless Communication
  • Electronic Instrumentation
  • Image Processing
  • Network Analysis
  • Signals and Systems

Research Book:

  • Dr. Mohana H S, Rajith Kumar B K, Uday J,Pattern Recognition Technique for Kannada Script Analysis” (Research Book) – Lambert Academic Publication, 2020 (ISBN: 978-620-2-55300-1)   

Number of Workshops / FDPs / SDPs / STTPs Attended/Conducted :    10

Conference / Journal Publications :

International Journal

  • Uday J, Rajithkumar B K, “A Novel Architecture of 32-bit Modulo 2n-1 Adder”, IJAST, 2020 
  • Uday J et al, “Implementation of 16 bit Hybrid modulo 2n-1 Adder”, IJERT, Vol 6, Issue 15,2018.
  • Uday J, G H Asha,  “Implementation of Modulo 2n+1 Adder and Multiplier”, IJECT,   Vol. 5, Issue 2, April-June 2014.

International Conference

  • Presented a paper on “An Automatic Drainage Overflow Detection System” in Recent Trends in Science & Technology ICRTST – 2020, organized ATME College of Engineering, Mysuru.
  • Presented a paper on  “A Novel Architecture of 32-bit Modulo 2n-1 Adder” in Global Conference on Advanced Smart and Sustainable Technologies in Engineering (GCASSTE)” Moodbiri
  • Uday J. et al “Edge Detection of Degraded Stone Inscription Kannada Character”, in Proceedings of IC3T-2016, Springer-AISC Series, Vol 542, pp 11-20, ISSN 2194-5357, 2017. (Indexed in SCOPUS, ISI Proceedings, EI-Compendex, DBLP, Google Scholar and Springer link)
  • Uday J. et al, “Read and recognition of old Kannada stone inscriptions characters using novel algorithm”, IEEE 2016, ISBN-978-1-4673-9825-2/15/$31.00 (2016). (Scopus Indexed)
  • Uday J, G H Asha, “Implementation  32-bit Area Efficient Hybrid Modulo 2n+1 Adder and Multiplier”, IEEE 2014, ISBN-978-1-4799-4190-2/14/$31.00 (2014). (Scopus Indexed)