The Department of Electronics & Communication Engineering, Mangalore Institute of Technology & Engineering, organized a two-day workshop on “From RTL to Prototype: Verilog Design & Verification for Hardware Innovation” on 2st and 22nd September 2026. The workshop was aimed at providing students with practical exposure to modern digital hardware design and verification workflows using Verilog HDL and industry-oriented Electronic Design Automation (EDA) tools. A total of 30 students participated in the workshop, gaining hands-on experience in RTL design, simulation, verification, and hardware implementation practices.
The resource person for the workshop was Dr. Madhushankara M, Associate Professor, Manipal School of Information Sciences, Manipal Academy of Higher Education (MAHE), Manipal. He has more than 15 years of academic experience in teaching and mentoring postgraduate students, with expertise in digital and mixed-signal design, Verilog HDL, RTL design, VLSI verification, and hardware implementation. An active researcher, Dr. Madhushankara has published more than 20 indexed research articles in reputed international journals and conferences. His doctoral research focused on developing an electrolarynx prototype for individuals who have lost their natural voice. He has also completed two research projects funded by the Department of Science and Technology (DST), Government of India, and has seven Indian patent applications, including one granted patent. His current research interests include portable biomedical devices, hardware accelerators for machine-learning applications, neuromorphic computing, energy-efficient digital and mixed-signal architectures, and VLSI design and verification.
The workshop provided participants with hands-on exposure to the ASIC/FPGA design and verification flow, Verilog HDL, Cadence environment, and self-checking testbench development. On the first day, students learned essential Linux commands, Cadence project setup, Verilog module structures, ports and data types, and the compilation, elaboration, and simulation of basic digital designs. They designed and simulated combinational circuits such as multiplexers, decoders, and ALUs, while developing testbenches for functional verification and waveform analysis. The sessions also introduced self-checking verification techniques, including directed and exhaustive stimulus generation, expected-output calculation, automated output comparison, PASS/FAIL reporting, error counting, and waveform-based debugging.
The second day focused on sequential logic verification and structured verification methodologies. Participants worked with clock and reset generation, blocking and non-blocking assignments, and edge-based stimulus while verifying counters, shift registers, and Finite State Machines (FSMs) under reset, normal, and boundary conditions. They also learned to develop test-case plans from specifications, implement reusable tasks and functions, create reference models for automated checking, and identify common RTL and testbench coding errors. The practical activities and mini-project approach enabled students to strengthen their understanding of industry-relevant RTL design and verification practices while bridging the gap between theoretical concepts and practical hardware prototyping.
The workshop was organized under the guidance of Dr. Vinayambika S Bhat, HoD – E&CE, Dean – Quality Assurance, and coordinated by, Dr. Sathisha, Associate Professor and Ms. Bhavya S, Senior Assistant Professor. The programme concluded successfully with active participation and hands-on engagement from students, providing them with valuable technical skills in Verilog-based RTL design, self-checking verification, and EDA tools, and enhancing their readiness for advanced work in VLSI and digital hardware design.