Workshop on “Chip Crafting: VLSI Layouts, Process Design Development for Microelectronic Systems”

The Electronics & Communication Engineering Students’ Association (ECSA) of the Electronics & Communication Engineering department, organized a Hands-on Workshop titled “Chip Crafting: VLSI Layouts, Process Design Development for Microelectronic Systems”, from 27^th to 29^th March 2025. The resource persons for the workshop were from KarMic Design Pvt. Ltd., Manipal: Mr. Sujay Kumar, Senior Design Engineer, Ms. Pavithra Shetty, Senior Design Engineer and Mr. Sriganesh Bhat, Design Engineer-2. Mr. Sujay’s expertise includes Audio modules, USB, Power management chips and module level layout design experience in – Low-Drop Out Voltage regulators (LDO), Switch Regulators (BUCK), Clock Generators (PLL), Reference Generators (Bandgap) & Bias Generators. Ms. Pavithra’s expertise area is Analog Mixed-Signal Layout Design. Mr. Bhat has good experience in the field of Analog mixed signal and RF layout design.

Around 45 students from third year of engineering, participated in the workshop that provided practical experience in CMOS VLSI layout designs. Participants explored new methods to design CMOS inverter layout with how NMOS and PMOS transistors work together to form an inverter. Layout optimization procedure helped to minimize area while ensuring correct connectivity and performance of the circuit. Identified the design rule constraints to ensure proper spacing, width and other rules to ensure manufacturability. Participants realized the parasitic effects because of capacitance and resistance which in turn will affect the performance of the circuit.

The workshop helped to get more exposure to Cadence tool, trade-offs between power, area and speed in layouts. The understanding of CMOS VLSI principles applicable to chip design jobs and importance of extraction and simulation for real-world performance validation. The workshop was highly beneficial for students and faculty members to gain industry-relevant expertise to strengthen their knowledge in VLSI technology for improved teaching and research.